therealpaulie
Newbie level 6
Hi,
I'll start by explaining what I want to achieve:
- I have a sine wave with variable frequency, in a wide range 0 - 200kHz
- I pass this sine wave through a ADC
- ADC sampling frequency is not high enough and I need more sample/sec after ADC
- In order to do this I use a IIR (4 order) with cutting frequency around 300KHz but with sampling frequency 20MHz -> sample available at every 50ns.
Everything is ok as concept.
My problem is that I have a 20MHz sampling rate for the IIR and only 0.3MHz cutting frequency. When implementing the filter in fix point arithmetic (for FPGA) I have to use 30 bits for adders and multipliers in order to reach a 15 bits accuracy. From b0..bn coefficients/multipliers i have small values 0.xxxxx and from a1..an coefficients/multipliers i have big values yyyyy.zzzz. In order to keep a good accuracy it results a yyyyy.xxxxx number (~ 2 x accuracy bits).
Working with 15-18 bits adders and multiplier is ok. But 30 bits is way to much.
I tried first with a Form I SOS (cascade) topology Matlab tools generates. I had around 8 multipliers and 8 adders for a 4order filter. At 24bit it looks ok. Though 8mult + 8add x 24 bits it's huge.
After that I tried with a Form II Transpose. At the beginning it looked perfect. Just 5 adders and 4 multipliers (+2 mult at lower frequency). But at 30-32 bits I still don't get a 15 accuracy for the output signal.
And in my FPGA there is not to much place (resources) left. So I have to be very very cheap with cells.
Is there a topology or a way to make such a filter as small as possible? Are there some documents on internet (links) which discuss such a problem.
Thanks,
Paul
I'll start by explaining what I want to achieve:
- I have a sine wave with variable frequency, in a wide range 0 - 200kHz
- I pass this sine wave through a ADC
- ADC sampling frequency is not high enough and I need more sample/sec after ADC
- In order to do this I use a IIR (4 order) with cutting frequency around 300KHz but with sampling frequency 20MHz -> sample available at every 50ns.
Everything is ok as concept.
My problem is that I have a 20MHz sampling rate for the IIR and only 0.3MHz cutting frequency. When implementing the filter in fix point arithmetic (for FPGA) I have to use 30 bits for adders and multipliers in order to reach a 15 bits accuracy. From b0..bn coefficients/multipliers i have small values 0.xxxxx and from a1..an coefficients/multipliers i have big values yyyyy.zzzz. In order to keep a good accuracy it results a yyyyy.xxxxx number (~ 2 x accuracy bits).
Working with 15-18 bits adders and multiplier is ok. But 30 bits is way to much.
I tried first with a Form I SOS (cascade) topology Matlab tools generates. I had around 8 multipliers and 8 adders for a 4order filter. At 24bit it looks ok. Though 8mult + 8add x 24 bits it's huge.
After that I tried with a Form II Transpose. At the beginning it looked perfect. Just 5 adders and 4 multipliers (+2 mult at lower frequency). But at 30-32 bits I still don't get a 15 accuracy for the output signal.
And in my FPGA there is not to much place (resources) left. So I have to be very very cheap with cells.
Is there a topology or a way to make such a filter as small as possible? Are there some documents on internet (links) which discuss such a problem.
Thanks,
Paul
