There is an adder which is two input and each input is of width [7:0]. The tl of the adder is as below and please see if it is a correct code of an adder. Can the following instansiation of the adder is correct if we want to tie the b input at one ?
How can the synthesis tool be instructed to synthesize only a ripple carry adder when the rtl of the adder is only the following rtl?
Code:
adder adder1 (a, 1'b1, En, out);
RTL of the adder whose module name is adder
Code:
module adder (a,b,en,out);
.................
.................
always (a or b or en )
begin
out=0
case (En)
1'b1: out = A+B;
1'b0 out = 0;
end
I have been following all of your posts in the ASIC & FPGA sub-forums, so tell me something frankly.........
Why do you think members will give you synth. RTL code for free for the various C-style pseudo code you are posting?
In the FPGA sub-forum I have given you links to dwnld a Xilinx FPGA tool where you can verify whether an RTL is synth or not. Use that, do some work yourself!
If you don't know VHDL/Verilog, then learn it !
I have been following all of your posts in the ASIC & FPGA sub-forums, so tell me something frankly.........
Why do you think members will give you synth. RTL code for free for the various C-style pseudo code you are posting?
In the FPGA sub-forum I have given you links to dwnld a Xilinx FPGA tool where you can verify whether an RTL is synth or not. Use that, do some work yourself!
If you don't know VHDL/Verilog, then learn it !