[SOLVED] If or else if? Which is better?

In a Verilog design, say that you have n (any number) completely
mutually exclusive events i.e. the events never occur simultaneously and
there is hence no priority associated with any event.In such a scenario,
what would be faster/simpler/less inferred hardware?


if (condition 1)
if (condition 2)
if (condition 3)
.
.
.
.
.
-------- OR ----------
if (condition 1)
else if (condition 2)
else if (condition 3)
.
.
.
.
.

In my opinion, I think the simple ifs would work out better since the
priority doesn't have to be checked and would infer less hardware.In C
or MATLAB, the opposite may be true because if condition 1 turns out to
be true then all remaining conditions can be skipped by using an else if.
My question ,however, is specific to VERILOG/VHDL.

Modern synthesis tools will synthesize mutually exclusive if statements (assuming the exclusivity is visible in compile time) into MUXs - and not priority encoders).

But I suggest you stick to a case statement...
Which is explicit and more readable.

In the case of synthesis, it should produce the same hardware
For simulation, you probably give yourself a performance penalty with just ifs because it has to check them all. But with today's processors, it's unlikely to be noticable.

Vhdl case statements do this. Verilog has pragmas for full case and parallel case, but this can lead to a simulation mismatch if your code doesn't match your assumptions.