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IF LOOP in Verilog A not working for 0.7

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atulkulkarni

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Hi All,

I am unable to enter this if loop,


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if (V(THRESHOLD1,GND)==0.7)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(VDD);dummy6=V(VDD);   end


However my if loop works when I compare it to any value other than 0.7...
FOR EX

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if (V(THRESHOLD1,GND)==0.6)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);


Please help . Is it a bug ??
 
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erikl

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Did you consider that the condition ==0.7 possibly is never reached? Why not use

Code Verilog - [expand]
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if (V(THRESHOLD1,GND)>=0.6)

 

atulkulkarni

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I have 5 to 6 if loops comparing different values like 0.6V,0.5V,0.4V. So cannot go with the above solution. I also tried with V(THRESHOLD1,GND)>0.699999 && V(THRESHOLD1,GND)<0.7000001 and its working..


Even in case statement I am not able to verify with 0.7 whereas other values are working
 

rahdirs

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Hi,

Can you post the complete code? Will try out at my end
 

atulkulkarni

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Code Verilog - [expand]
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`include "constants.vams"
`include "disciplines.vams"
module TG(VDD,GND,GAIN,OFFSET,TRIM,THRESHOLD);
 
input GAIN,VDD,GND,OFFSET,THRESHOLD;
output [15:0] TRIM;
 
electrical GAIN,VDD,GND,OFFSET,THRESHOLD;
electrical[15:0] TRIM;
electrical gnd;
ground gnd;
 
 
 
real gain_1;
real offset_1;
real total;
real final;
real flag;
real threshold_1;
integer i;
integer number;
real dummy1,dummy2,dummy3,dummy4,dummy5,dummy6;
 
analog begin
@ (initial_step) begin
flag=0;
dummy1=0;dummy2=0;dummy3=0;dummy4=0;dummy5=0;dummy6=0;
end
 
gain_1=V(GAIN);
offset_1=V(OFFSET);
threshold_1=V(THRESHOLD);
total=gain_1+offset_1;
 
if(total<0)
    begin
    total=total*(-1);
    flag=1;
    end
 
if(total<=0.255)
    begin
    final=total*1000;
    number=final;
    $display("final = %f" , final);
    end
 
else
    begin
    final=total*100;
    $display("final = %f" , final);
    end
 
generate i (0,8,1)
    begin
 
    if((number%2)==0)
        begin
        V(TRIM[i])<+0;
        $display(" not entered");
        $display("value of final %d",number);
        number=(number)/2;
        end
    else
    begin
    V(TRIM[i])<+V(VDD);
    $display(" entered");
    $display("value of final %d",number);
    number=(number-1)/2;
    end
//if(flag==1)
//V(TRIM[8])<+1.8;
end
if(flag==1)
V(TRIM[8])<+V(VDD);
    $display(" threshold_1 = %f",threshold_1);
 
 
case(threshold_1)
3.3:begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
    dummy1=V(GND); dummy2=V(GND);dummy3=V(GND);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
2.5:begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(GND); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
2:begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(GND); dummy2=V(VDD);dummy3=V(GND);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
1.8:begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
 dummy1=V(GND); dummy2 =V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
1.5:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
    dummy1=V(VDD); dummy2=V(GND);dummy3=V(GND);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
1.4:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
1.3:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(VDD);end
1.2:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(VDD);dummy6=V(GND);end
1.1:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(VDD);dummy6=V(VDD);end
1:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(GND);dummy6=V(GND);end
0.9:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(GND);dummy6=V(VDD);end
0.8:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(VDD);dummy6=V(GND);$display(" entered zero.eightvolt");end
0.7:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(VDD);dummy6=V(VDD);   $display(" entered zero.sevenvolt %f",threshold_1);end
0.6:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
0.5:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(VDD);end
0.4:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(VDD);dummy6=V(GND);end
default : begin 
/*V(TRIM[14])<+V(VDD);
V(TRIM[13])<+V(VDD);
V(TRIM[12])<+V(VDD);
V(TRIM[11])<+V(VDD);
V(TRIM[10])<+V(VDD);
V(TRIM[9])<+V(VDD);*/
$display(" Intermediate values %f",threshold_1);
V(TRIM[14])<+dummy1;
V(TRIM[13])<+dummy2;
V(TRIM[12])<+dummy3;
V(TRIM[11])<+dummy4;
V(TRIM[10])<+dummy5;
V(TRIM[9])<+dummy6;
end
endcase
 
/*if (threshold_1>0.6999999 && threshold_1<0.70000001)
begin
 V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
//V(TRIM[14])<+V(VDD)*0.5-V(VDD)*0.5; V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD)*0.5-V(VDD)*0.5;V(TRIM[11])<+V(VDD)*0.5-V(VDD)*0.5;V(TRIM[10])<+V(VDD)*(2/3);V(TRIM[9])<+V(VDD);
//V(TRIM[14])<+V(TRIM[14])-V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(TRIM[12])-V(VDD);V(TRIM[11])<+V(TRIM[11])-V(VDD);V(TRIM[10])<+V(TRIM[10])-V(VDD);V(TRIM[9])<+V(TRIM[9])-V(VDD);
    $display(" entered if loop %f",threshold_1);
end*/
 
 
 
end
endmodule





here case statement is not working for 0.7 .... Replaced case with if statements and facing same issue........ U can use vpwl to verify

- - - Updated - - -

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// VerilogA for pradeep_lib, sorabh, veriloga
 
`include "constants.vams"
`include "disciplines.vams"
`define BITS 8
module T_G(VDD,GND,GAIN,OFFSET,TRIM,THRESHOLD);
 
input GAIN,VDD,GND,OFFSET,THRESHOLD;
output [15:0] TRIM;
 
electrical GAIN,VDD,GND,OFFSET,THRESHOLD;
electrical[15:0] TRIM;
electrical gnd;
ground gnd;
 
 
 
real gain_1;
real offset_1;
real total;
real final;
real flag;
real threshold_1;
integer i;
integer number;
real dummy1,dummy2,dummy3,dummy4,dummy5,dummy6;
 
analog begin
@ (initial_step) begin
flag=0;
dummy1=0;dummy2=0;dummy3=0;dummy4=0;dummy5=0;dummy6=0;
end
 
gain_1=V(GAIN);
offset_1=V(OFFSET);
threshold_1=V(THRESHOLD);
total=gain_1+offset_1;
 
if(total<0)
    begin
    total=total*(-1);
    flag=1;
    end
 
if(total<=0.255)
    begin
    final=total*1000;
    number=final;
    $display("final = %f" , final);
    end
 
else
    begin
    final=total*100;
    $display("final = %f" , final);
    end
 
generate i (0,8,1)
    begin
 
    if((number%2)==0)
        begin
        V(TRIM[i])<+0;
        $display(" not entered");
        $display("value of final %d",number);
        number=(number)/2;
        end
    else
    begin
    V(TRIM[i])<+V(VDD);
    $display(" entered");
    $display("value of final %d",number);
    number=(number-1)/2;
    end
//if(flag==1)
//V(TRIM[8])<+1.8;
end
if(flag==1)
V(TRIM[8])<+V(VDD);
    $display(" threshold_1 = %f",threshold_1);
 
if (threshold_1==3.3)
begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
    dummy1=V(GND); dummy2=V(GND);dummy3=V(GND);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
else if(threshold_1==2.5)
begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(GND); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
 
else if(threshold_1==2)
begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(GND); dummy2=V(VDD);dummy3=V(GND);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
else if(threshold_1==1.8)
begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
 dummy1=V(GND); dummy2 =V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
 
else if(threshold_1==1.5)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
    dummy1=V(VDD); dummy2=V(GND);dummy3=V(GND);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
 
else if(threshold_1==1.4)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
 
else if(threshold_1==1.3)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(VDD);end
 
 
else if(threshold_1==1.2)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(VDD);dummy6=V(GND);end
 
 
else if(threshold_1==1.1)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V(VDD);dummy6=V(VDD);end
 
 
else if(threshold_1==1)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(GND);dummy6=V(GND);end
 
 
else if(threshold_1==0.9)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(GND);dummy6=V(VDD);end
 
 
else if(threshold_1==0.8)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(VDD);dummy6=V(GND);$display(" entered zero.eightvolt");end
 
else if(threshold_1==0.7)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(VDD);dummy6=V(VDD);   $display(" entered zero.sevenvolt %f",threshold_1);end
 
else if(threshold_1==0.6)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(GND);end
 
 
else if(threshold_1==0.5)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND);dummy6=V(VDD);end
 
else if(threshold_1==0.4)
begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(VDD);dummy6=V(GND);end
 
else 
 
begin 
 
 
$display(" Intermediate values %f",threshold_1);
V(TRIM[14])<+dummy1;
V(TRIM[13])<+dummy2;
V(TRIM[12])<+dummy3;
V(TRIM[11])<+dummy4;
V(TRIM[10])<+dummy5;
V(TRIM[9])<+dummy6;
end
 
 
 
 
end
endmodule





Please check if condtion with 0.7 ...... Try using vpwl for input "THRESHOLD" .I tried with if (threshold1>0.699999 && threshold1<0.7000001) and its working
 
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atulkulkarni

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Code:
`include "constants.vams"
`include "disciplines.vams"
module TG(VDD,GND,GAIN,OFFSET,TRIM,THRESHOLD);

input GAIN,VDD,GND,OFFSET,THRESHOLD;
output [15:0] TRIM;

electrical GAIN,VDD,GND,OFFSET,THRESHOLD;
electrical[15:0] TRIM;
electrical gnd;
ground gnd;



real gain_1;
real offset_1;
real total;
real final;
real flag;
real threshold_1;
integer i;
integer number;
real dummy1,dummy2,dummy3,dummy4,dummy5,dummy6;

analog begin
@ (initial_step) begin
flag=0;
dummy1=0;dummy2=0;dummy3=0;dummy4=0;dummy5=0;dummy 6=0;
end

gain_1=V(GAIN);
offset_1=V(OFFSET);
threshold_1=V(THRESHOLD);
total=gain_1+offset_1;

if(total<0)
begin
total=total*(-1);
flag=1;
end

if(total<=0.255)
begin
final=total*1000;
number=final;
$display("final = %f" , final);
end

else
begin
final=total*100;
$display("final = %f" , final);
end

generate i (0,8,1)
begin

if((number%2)==0)
begin
V(TRIM[i])<+0;
$display(" not entered");
$display("value of final %d",number);
number=(number)/2;
end
else
begin
V(TRIM[i])<+V(VDD);
$display(" entered");
$display("value of final %d",number);
number=(number-1)/2;
end
//if(flag==1)
//V(TRIM[8])<+1.8;
end
if(flag==1)
V(TRIM[8])<+V(VDD);
$display(" threshold_1 = %f",threshold_1);


case(threshold_1)
3.3:begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(GND); dummy2=V(GND);dummy3=V(GND);dummy4=V(GND);dummy5=V (GND);dummy6=V(GND);end
2.5:begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(GND); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V (GND);dummy6=V(GND);end

2:begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(GND); dummy2=V(VDD);dummy3=V(GND);dummy4=V(GND);dummy5=V (GND);dummy6=V(GND);end

1.8:begin V(TRIM[14])<+V(GND); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(GND); dummy2 =V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V(GND); dummy6=V(GND);end
1.5:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(GND);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(GND);dummy4=V(GND);dummy5=V (GND);dummy6=V(GND);end
1.4:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V (GND);dummy6=V(GND);end
1.3:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V (GND);dummy6=V(VDD);end
1.2:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V (VDD);dummy6=V(GND);end
1.1:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(GND);dummy5=V (VDD);dummy6=V(VDD);end
1:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V (GND);dummy6=V(GND);end
0.9:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V (GND);dummy6=V(VDD);end
0.8:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V (VDD);dummy6=V(GND);$display(" entered zero.eightvolt");end
0.7:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V (VDD);dummy6=V(VDD); $display(" entered zero.sevenvolt %f",threshold_1);end
0.6:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V (GND);dummy6=V(GND);end
0.5:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(GND);V(TRIM[9])<+V(VDD);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V (GND);dummy6=V(VDD);end
0.4:begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(VDD);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(GND);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(GND);
dummy1=V(VDD); dummy2=V(VDD);dummy3=V(VDD);dummy4=V(GND);dummy5=V (VDD);dummy6=V(GND);end
default : begin 
/*V(TRIM[14])<+V(VDD);
V(TRIM[13])<+V(VDD);
V(TRIM[12])<+V(VDD);
V(TRIM[11])<+V(VDD);
V(TRIM[10])<+V(VDD);
V(TRIM[9])<+V(VDD);*/
$display(" Intermediate values %f",threshold_1);
V(TRIM[14])<+dummy1;
V(TRIM[13])<+dummy2;
V(TRIM[12])<+dummy3;
V(TRIM[11])<+dummy4;
V(TRIM[10])<+dummy5;
V(TRIM[9])<+dummy6;
end
endcase

/*if (threshold_1>0.6999999 && threshold_1<0.70000001)
begin
V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD);
//V(TRIM[14])<+V(VDD)*0.5-V(VDD)*0.5; V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD)*0.5-V(VDD)*0.5;V(TRIM[11])<+V(VDD)*0.5-V(VDD)*0.5;V(TRIM[10])<+V(VDD)*(2/3);V(TRIM[9])<+V(VDD);
//V(TRIM[14])<+V(TRIM[14])-V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(TRIM[12])-V(VDD);V(TRIM[11])<+V(TRIM[11])-V(VDD);V(TRIM[10])<+V(TRIM[10])-V(VDD);V(TRIM[9])<+V(TRIM[9])-V(VDD);
$display(" entered if loop %f",threshold_1);
end*/



end
endmodule


here case statement is not working for 0.7 .... Replaced case with if statements and facing same issue........ U can use vpwl to verify
 

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