If latch based clock gating is used then setup time is always satisfied?

[megastar007]

if latch based clock gating is used then setup time is always satisfied ?

 

[sameer_dlh25]

Re: Clock gating

Hi megastar007,

I hope I am getting your question right.

If a clock gating signal is passed a latch which is active when clock is low and output
of this signal is used as clock gating signal. On clock gating element clock gating setup and hold are met by design.
I mean after this in your gated clock you will get the complete pulse with. Here it is assumed that clock at clock gating element (e.g. an And gate) and latch is balanced in layout.
Usually special cells are used for this purpose.:|

 

[megastar007]

Re: Clock gating

i read some doc saying that
" clock gating occurs during elaboration,before clock waveforms exist.This makes it impossible to directly check during clock-gate insertion whether a tsetup time at clock gate can be met later i.e. during logic synthesis. if latch based clock gating is used,the setup condition is always satisfied otherwise by using latch free clock gating,the setup condition is not always satisfied.


So,Why setup condition is always satisifed by using latch based clock gating ?