Sorry i have a logic for when en_logic = 1
Code VHDL - [expand] |
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| not_gen_logic : if (en_logic = '0') generate
in1 <= rx_inp1;
in2 <= rx_inp2;
in3 <= rx_inp3;
in4<= rx_inp4;
end generate;
-- input to some filter
gen_logic : if (en_logic = '1') generate
inst_filter : filter port map (rx_inp1, rx_inp2, rx_inp3, rx_inp4,out1,out2,out3,out4);
in1 <= out1;
in2 <= out2;
in3 <= out3;
in4 <= out4;
end generate; |
I expect synthesizer to generate both logic but result is muxed at output