Jul 28, 2011 #1 T titanic Newbie level 6 Joined Jun 23, 2010 Messages 12 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,364 Hi, i am wondering which of the following verilog snippet is more efficient in terms of speed and area. --------CODE 1 reg [4:0] A if(A[4:0] = 5'b11111) jobs1 else if(A[3:0] = 4'b1111) jobs2 else if(A[2:0] = 3'b111) jobs3 else ifA[1:0] = 2'b11) jobs4 else if(A[0] = 1'b1) jobs5 --------- CODE 2 reg [4:0] A Case (A) 5'b11111 : jobs1 5'b01111 : jobs2 5'b00111 : jobs3 5'b00011 : jobs4 5'b00001 : jobs5 endcase would eliminating "default" be good or bad for the case statement given above? Thanx in advance
Hi, i am wondering which of the following verilog snippet is more efficient in terms of speed and area. --------CODE 1 reg [4:0] A if(A[4:0] = 5'b11111) jobs1 else if(A[3:0] = 4'b1111) jobs2 else if(A[2:0] = 3'b111) jobs3 else ifA[1:0] = 2'b11) jobs4 else if(A[0] = 1'b1) jobs5 --------- CODE 2 reg [4:0] A Case (A) 5'b11111 : jobs1 5'b01111 : jobs2 5'b00111 : jobs3 5'b00011 : jobs4 5'b00001 : jobs5 endcase would eliminating "default" be good or bad for the case statement given above? Thanx in advance
Jul 29, 2011 #2 Z zhipeng Member level 1 Joined Apr 9, 2009 Messages 36 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Location USA Activity points 1,573 They are behaviorally equal. After synthesis, the two will probably become structurally equal too. Eliminating the default else in CODE 1 or the default: in CODE 2 could be bad for you, if you don't want latches being synthesized for the codes...
They are behaviorally equal. After synthesis, the two will probably become structurally equal too. Eliminating the default else in CODE 1 or the default: in CODE 2 could be bad for you, if you don't want latches being synthesized for the codes...