IEEE standard for verilog registrar tranfer level synthesis

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ASIC_int

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What is "IEEE standard for verilog registrar tranfer level synthesis" document? What does it write? What is the OVJECTIVE of this document.
What is the lastest version of it ? Is 1364.1-2002 the latest version?

What is the other IEEE documents that is relavant to a RTL Design Engineer?
 

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