Ideal Current Mode Class D (CMCD) question

[pYrana13]

Hi all,

I am designing this CMCD-PA using Agilent ADS. I would like to know, why did the voltage at output load (R4) form a half sinusoidal shape?
Shouldn't it be a full sinusoidal waveform, similar to the current at R4??

You can refer to my schematic and the output in the attachment below.

TQ

 

[FvM]

The "voltage at the output load" is also the voltage at the output transistor. It's hold at zero while the switch is closed by nature of the circuit, so the flat bottom line isn't surprizing.

 

[mtwieg]

Each switch has a half sine wave shape on it, the voltage appearing across the load will thus be a full sine wave.