grubby23
Junior Member level 3
Weird Timing Report
Hi
In my design, I used ICON & ILA components for debugging. For proper timing results I would like to exclude those components as in the static timing report
it looks like as if the critical path is within these components. However, when removing those debugging cores the timing report does not output a critical path anymore. It looks as follows:
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
rx | 0.481(R)| 0.566(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
dbg_reg1<0> | 6.185(R)|clk_BUFGP | 0.000|
dbg_reg1<1> | 5.938(R)|clk_BUFGP | 0.000|
....
reset | 11.196(R)|clk_BUFGP | 0.000|
tx | 7.281(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 23.847| | | |
---------------+---------+---------+---------+---------+
Anyone an idea was has happened? The top-modul of my design does not
output any result, as until now I used the JTAG Interface for debugging. Could this now be a problem when I got rid of the debug units?
Thanks
Hi
In my design, I used ICON & ILA components for debugging. For proper timing results I would like to exclude those components as in the static timing report
it looks like as if the critical path is within these components. However, when removing those debugging cores the timing report does not output a critical path anymore. It looks as follows:
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
rx | 0.481(R)| 0.566(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
dbg_reg1<0> | 6.185(R)|clk_BUFGP | 0.000|
dbg_reg1<1> | 5.938(R)|clk_BUFGP | 0.000|
....
reset | 11.196(R)|clk_BUFGP | 0.000|
tx | 7.281(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 23.847| | | |
---------------+---------+---------+---------+---------+
Anyone an idea was has happened? The top-modul of my design does not
output any result, as until now I used the JTAG Interface for debugging. Could this now be a problem when I got rid of the debug units?
Thanks