Hey, were you able to solve the issue?? I'm facing the same problem...
I used -allow_undefined_module as suggested by the error message.
So, its not giving any errors now... but I don't see the FRAM being used in my top level module.
Thanks.
---------- Post added at 05:38 ---------- Previous post was at 04:18 ----------
Hi,
I should rephrase the question.... I have created the FRAM and ILM views for the module (to be integrated in the 'top' level).
I don't know how to integrate the FRAM/ILM views while importing the top_level module's verilog file.
Currently, I am including the path of the module_LIB as a reference library - but yet, while reading the module instantiation in the top level netlist, it throws an error {module not found}. This error disappears when I use -allow_undefined_module with read_verilog.
Thanks