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Icarus Verilog doesn't support generate?

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IBNobody

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icarus verilog generate

I'm trying to work through some of the examples found in Samir Palnitkar's "Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition".

I'm using Icarus Verilog since it's free.

The problem I'm running into is that Icarus doesn't seem to support generate. It won't even recognize "genvar". This is odd because it's supposedly Verilog 2001 complient.

I did a 'net search, and I didn't see anything that would indicate Icarus didn't work. Am I missing something?

Are there better free & length unrestricted Verilog simulators out there?

- Nobody
 

r_p_sanna

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icarus verilog genvar

if i m not mistaken, bluehdl is a simulator which might help solve your problem
 

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