delon
Junior Member level 2
Hello, please help me to clarify this: why the control signal (which is the input to the counter) from the master controller is asserted high 1 cycle AFTER SCL output is asserted high? On the other hand, the control signal is asserted low at the same clock cycle when SCL output become low.
From my understanding, if the above is true then there will be no symmetry in the SCL clock as SCL high period will be larger than SCL low period. Please help me find out where I am making the mistake.
Thanks
From my understanding, if the above is true then there will be no symmetry in the SCL clock as SCL high period will be larger than SCL low period. Please help me find out where I am making the mistake.
Thanks