PA3040 said:Please explain what is the meaning of general call condition in I2C
The general call address is used to do broad cast over the entire bus. It addresses all the slaves connected to the bus irrespective of their programmed address. But it is not mandatory that all the connected devices should respond to general call addressing. The devices that not interested in general call can ignore the same. But those devices make use of general call should acknowledge properly. The byte follows the general call address usually define what action needs to be taken by the slaves in response to the call. The command in the second byte is interpreted based on the value of its LSB. If LSB is zero, the following commands are defined.
00000110 (0x06): When receiving this command, all devices should reset and take in the programmable part of their address.
00000100 (0x04): Take in the programmable part of the address, but do not reset
Other values in this scenario are undefined and should be ignored by slaves.
When the LSB of the second byte in general call is one , it means that this call is made by a hardware master device who does not have any prior information of the connected slave addresses. In this case the master does the call with its own address so that the slaves can identify the source of the message.
Above picture shows simulator how read & write to EEPROM using I2C.here slave address is 4 bits but manual says it is 7bits. then how can we load slave address to SSPBUF register
as well as please advice to me can we simulate I2C using MPLAB SIM
as per my picture. let me know the address that i want use here
this is 24c32 eeprom 1010 A1 A2 A3[
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code; for the 24C32 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
How is your particular device's external address lines configured?
status equ 0x03 ;bank 0
intcon equ 0x8b ;bank 0
pir1 equ 0x0c ;bank 0
sspbuf equ 0x13 ;bank 0
sspadd equ 0x93 ;bank 1
sspcon equ 0x14 ;bank 0
sspstat equ 0x94 ;bank 1
trisc equ 0x87 ;bank 1
portc equ 0x07 ;bank 0
sspcon2 equ 0x91 ;bank 1
i2c_addres equ b'10100000' ;24c32 address
start call sys_init
clrwdt
goto main
main call i2c
i2c bcf intcon,7
call i2c_start
movlw i2c_addres
addlw b'11111110'
call tx_byte
call is_ackn_rx
movlw 0x00
call tx_byte
call is_ackn_rx
call i2c_restart
movlw i2c_addres
iorlw b'00000001'
call tx_byte
call is_ackn_rx
i2c_start bsf status,5
bsf sspcon2,0
bcf status,5
bcf pir1,3
btfss pir1,3
goto $-1
bcf pir1,3
return
i2c_restart bsf status,5
bsf sspcon2,1
bcf status,5
bcf pir1,3
btfss pir1,3
goto $-1
bcf pir1,3
return
tx_byte clrwdt
bcf pir1,3
movwf sspbuf
is_tx btfss pir1,3
goto is_tx
bcf pir1,3
return
is_ackn_rx bsf status,5
ack_rx_loop clrwdt
btfsc sspcon2,6
goto ack_rx_loop
bcf status,5
return
sys_init bsf status,5
movlw b'11111011'
movwf trisc
bcf sspstat,7
; bsf sspstat,3
bcf status,5
movlw b'00101000'
movwf sspcon
return
end
Dear BigDog Thanks for reply
it does not show how configure external pins, it show configure SCL and SDA line only
can you see any error the program I wrote for I2C
Code:status equ 0x03 ;bank 0 intcon equ 0x8b ;bank 0 pir1 equ 0x0c ;bank 0 sspbuf equ 0x13 ;bank 0 sspadd equ 0x93 ;bank 1 sspcon equ 0x14 ;bank 0 sspstat equ 0x94 ;bank 1 trisc equ 0x87 ;bank 1 portc equ 0x07 ;bank 0 sspcon2 equ 0x91 ;bank 1 [COLOR="#FF0000"]i2c_addres equ b'10100000' ;24c32 address[/COLOR] start call sys_init clrwdt goto main main call i2c i2c bcf intcon,7 call i2c_start movlw i2c_addres addlw b'11111110' call tx_byte call is_ackn_rx movlw 0x00 call tx_byte call is_ackn_rx call i2c_restart movlw i2c_addres iorlw b'00000001' call tx_byte call is_ackn_rx i2c_start bsf status,5 bsf sspcon2,0 bcf status,5 bcf pir1,3 btfss pir1,3 goto $-1 bcf pir1,3 return i2c_restart bsf status,5 bsf sspcon2,1 bcf status,5 bcf pir1,3 btfss pir1,3 goto $-1 bcf pir1,3 return tx_byte clrwdt bcf pir1,3 movwf sspbuf is_tx btfss pir1,3 goto is_tx bcf pir1,3 return is_ackn_rx bsf status,5 ack_rx_loop clrwdt btfsc sspcon2,6 goto ack_rx_loop bcf status,5 return sys_init bsf status,5 movlw b'11111011' movwf trisc bcf sspstat,7 ; bsf sspstat,3 bcf status,5 movlw b'00101000' movwf sspcon return end
in software you have to send address like A0 for 1st eeprom A1 for second like that..
like this depending on the software you send to slave that particular slave will talk to master controller...
hope you understand.
As per above, that mean we not need any hardware configuration for A0 , A1 , A2 ( this mean this pin renaming open , am I right)?
A2 A1 A0
0 0 0 (Here device address becomes 1010000 (7 bit address)
0 0 1 (Here device address becomes 1010001 (7 bit address)
0 1 0 (Here device address becomes 1010010 (7 bit address)
0 1 1 (Here device address becomes 1010011 (7 bit address)
1 0 0 (Here device address becomes 1010100 (7 bit address)
1 0 1 (Here device address becomes 1010101 (7 bit address)
1 1 0 (Here device address becomes 1010110 (7 bit address)
1 1 1 (Here device address becomes 1010111 (7 bit address)
So I am a little bit confused about the basic function of this modeI have some ideas, what this mode could be, but I am not shure:
Lets assume, that in this mode the I2C module is disabled (SSPSR does
not shift, WCOL, SSPOV, BF (and the other flags) are not touched .. and
so on...). The only part of the I2C module, that is enabled is the START
and the STOP detector. Both trigger an interrupt. All I2C bus operations
are done through software, manipulating PORTC. --- But if one realizes a
I2C master doing so, START/STOP interrupts are not nessecary, because
the I2C master drives START/STOP. It could be helpful, if one whishes to
realize a I2C slave in software, but this way this mode would not be
called a "master mode".
The I2C Firmware controlled Master mode (slave idle), is the most common I2C mode used by a MCU. The MCU is designated as Master of the I2C bus and is responsible for generating clocking and issuing commands. The master of an I2C must generate the clock signal, the slave cannot which is why it is referred to as "idle". The transmission and clock signal are started when data is written to SSPBUF, the BF bit is set as well and cleared once the byte has been transmitted.
There are some I2C which can act as Master of an I2C bus, however most peripheral I2C devices act as slaves. One common exception is connecting two or more PICs or other MCUs together via the I2C bus as a communications channel one MCU is usually delegated as Master and the rest of the MCUs slaves.
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