19- There are two Microcontrollers on one I2C Bus (Both having inbuilt I2C) and one slave. The 1st micro controller having address 01, slave address is 02, and other microcontroller address is 03.
Now the 1st microcontroller tried to access the slave at the exact time the 2nd microcontroller tried to access the 1st microcontroller. Who would win arbitration? Assume that the start bit occurred exactly at the same time.
Now the 1st microcontroller tried to access the slave at the exact time the 2nd microcontroller tried to access the 1st microcontroller. Who would win arbitration?
You say "at the exact time".
I say this is just an theoretical case.
There will be no problem.
The I2C arbitration (when implemented as in the I2C standards) works as folows.
* Each master send´s out it´s data and reads back the state of the signal line.
* A bus error is detected when the master is in "write_mode" and sends out a "1", but reads in a "0".
* The master that detects the mismatch should immediately disconnect from bus.
* The other master may continue communication.
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But when both masters send out the same data at exactly the same time no one will (and needs to) detect the problem, The slave will respond and both masters will receive the same data.
This situation is not realistic ... it just gives the answer to your question.
Hello KlauST, Thank you for your reply, it's very helpful.
But my question was a bit different.
It has two conditions;
a) the 1st microcontroller(Addr-01H) tried to access the slave(Addr-02H)
b)2nd microcontroller(Addr-03H) tried to access the 1st microcontroller
Despite of the unrealistic assumption of exactly simultaneous start, you can easily figure it out. Just look at the address bytes. At the first different bit value, the master sending a low level wins. In this case 01 wins over 02.
The I2C arbitration (when implemented as in the I2C standards) works as folows.
* Each master send´s out it´s data and reads back the state of the signal line.
* A bus error is detected when the master is in "write_mode" and sends out a "1", but reads in a "0".
* The master that detects the mismatch should immediately disconnect from bus.
* The other master may continue communication.
Hello FvM, I agree with the answer, but theoretically the condition exists. So according to the answer the master sending '0' first wins arbitration. So according to my question the 2nd Microcontroller wins and keeps on transmitting the frame.
But as the 1st microcontroller lost the arbitration then according to the I2C bus-specification it will go into slave-mode in which it will only be released when a StopBit Or StartBit is met, So the 1st Microcontroller won't give ACK.
That makes it more confusing. Does it have any counter measures for this particular condition(according to the I2C Bus-Spec)?
That's no arbitration problem. It's the question how the "1st microcontroller" is switching between master and slave role, an application layer problem.
By the way, which real world application involves the sketched configuration?
Actually i am using two master microcontrollers(MDUC812) having inbuilt I2C.
I just wanted to know that If there isn't any hardware configuration taking care of this for me then i have to add some extra code if this condition occurs(Just In Case).