i2c controller opencores

[mishanya]

Hello. Anyone used i2c controller available at opencores?
I need to organize data exchange between Master and Slave controllers...if somebody have ready decision...share...please!
Sorry for my bad English

 

[yanzixuan]

Hello. Anyone used i2c controller available at opencores?
I need to organize data exchange between Master and Slave controllers...if somebody have ready decision...share...please!
Sorry for my bad English

I wrote one by myself.
Basically the core is from OPENCORE seems no problem.

 

[mishanya]

I beginner in this area. And about work it is necessary to give results to the teacher. Can share simple examples master and slave controller on the basic of a core from opencores?

 

[yanzixuan]

Sorry that the core I wrote myself is a part of company's project. So I can't not show you.
But the master part from Opencore is enough.
and your can get the Slave part as:24LC16B.v.//google it
It's a behaviors simulation model as a I2C slave. So if you figure out how to use the master part.
connect it with the slave model, then you can do a test bench for vitrification

 

[mishanya]

I try to Simulate Behavioral model in Xilinx ISE Simulator for project i2c from opencores VHDL and i has seen this ERROR: Default port map for entity i2c_master_bit_ctrl
to component i2c_master_bit_ctrl connects
UNSIGNED type local port CLK_CNT of the
component to UNSIGNED type port of the
entity.
anyone know what is this?structure of project is original.
I'm sorry for my bad English