I2C Communication Link- Synthesis

Hi all, Can any one solve my problem??? While synthesizing following code I'm getting following error::

""""Statements in this 'always' block are outside the scope of synthesis policy. Only an 'if' statement is allowed at the top level in this always block.""""


always @(negedge scl or posedge sto or posedge temp)

if (temp)
begin
state <= #1 idle; // reset statemachine
sda_o <= #1 1'b1;
ld <= #1 1'b1;
end
else
begin
// initial settings
sda_o <= #1 1'b1;
ld <= #1 1'b0;

case(state)

idle: // idle state
if (acc_done && my_adr)
begin
state <= #1 slave_ack;
rw <= #1 sr[0];
sda_o <= #1 1'b0; // generate i2c_ack

#2;
if(debug && rw)
$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
if(debug && !rw)
$display("DEBUG i2c_slave; command byte received (write) at %t", $time);

if(rw)
begin
mem_do <= #1 mem[mem_adr];

if(debug)
begin
#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr, " at %t", $time);
#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x, [3]=%x", mem[4'h0], mem[4'h1], mem[4'h2], mem[4'h3]);
end
end
end

slave_ack:
//begin
if(rw)
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
begin
state <= #1 get_mem_adr;
ld<= #1 1'b1;
end

get_mem_adr: // wait for memory address
if(acc_done)
begin
state <= #1 gma_ack;
mem_adr <= #1 sr; // store memory address
sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address

if(debug)
#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
end

gma_ack:
begin
state <= #1 data;
ld <= #1 1'b1;
end

data: // receive or drive data
//begin
if(rw)
begin
sda_o <= #1 mem_do[7];
if(acc_done)
begin
state <= #1 data_ack;
mem_adr <= #2 mem_adr + 8'h1;
sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read

if(rw)
begin
#3 mem_do <= mem[mem_adr];

if(debug)
#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr , " at %t", $time);
end

if(!rw)
begin
mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory

if(debug)
#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
end
end
end

data_ack:
//begin
//ld <= #1 1'b1;
if(rw)
begin
if(sr[0])
begin
state <= #1 idle;
sda_o <= #1 1'b1;
end
else
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
end
else
begin
state <= #1 data;
sda_o <= #1 1'b1;
end
endcase
end

which software u r using and which mc

Hi, I'm using Synopsys Synthesis tool for synthesis.