I2C bus - 1.2us glitch is it correct or not?

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EDA_hg81

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glitch + i2c

I am using I2C bus to write data to EEPROM based on FPGA. I am running I2C at 100K HZ

During every acknowledge period, I found a single 1.2us glitch.

Are they correct or not?

Thanks.
 

i2c glitch

During SCL=0, it would be allowed.
 

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    EDA_hg81

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Re: I2C bus and glitch

Thank you FVM.

Is this glitch is from EEPROM ?

I am wondering if the I/O enable function of FPGA make glitch happen ?

Can we avoid this?

Thanks.
 

I2C bus and glitch

As a basic question: Is the communication logical correct according to the I2C standard? I can't see this from your post.

You are also able to see, which side is sending the glitch. Usually the SDA output low leves are different by a small amount. If not, you can connect a small series resistor to one output.
 

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