There are ways of doing it at RTL level but it's quite cumbersome, here you have an extract of the COMP.ARCH.FPGA newsgroup:
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Article: 28365
Subject: Re: grey code counters
Date: Wed, 10 Jan 2001 09:20:04 -0800
Here are my notes:
Grey-Coded Addresses
Only one bit/address changes at any time
Therefore no glitches from the identity comparator
Implementation:
Build binary counter
Generate XOR of two adjacent D-inputs
(that is the trick ! Don't use the binary Q, use the binary D)
Feed these XORs to a register = Grey !
MSB binary = MSB Grey
Advantage: very fast and easily epandable.
Yes, it wastes flip-flops. But I think it is still the most compact
(cheapest) solution in Virtex, where one CLB implements two bits, since it
has 4 flip-flops.
I tried various other ways, and -while they did not waste flip-flops- they
were no cheaper.
BTW: You can of course use the simultaneous binary output "for free".
You can also run the counter in both directions "for free".
I will gladly accept a more compact solution.
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There is more info in the newsgroup about it so have a look.
Why do you need a grey counter? Low noise, low power consumption?I don't like them what can I say.
Regards,
Maestor