I/P reference clk and feedback clk offset in PLL

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SRIDHARAN619

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HI all ,

i have designed PLL. After locking input reference clk and feedback clk offset is in 2nm. how can i minimized this offset into some ps range. ref freq is 10MHz and o/p freq is 40MHz. and how can i identify problem behid this issue?
 

Offset is 2nS? This offset is found in simulation or measurement?
 
Yes, Offset is 2nS This offset is found in simulation.
 

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