Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] I/O signaling standards supported in Xilinx I/O blocks

Status
Not open for further replies.
A

ahmadagha23

Guest
Newbie level 1
I/O signaling standards

Hi
1-where can I find some detailed information about I/O signaling standards supported in Xilinx I/O blocks?
2- Is it true that the bigger number for "speed Grade" in FPGAs means the better quality and in CPLDs means the lower quality?
regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top