I/O pad design for buck converter in Cadence.

[arunkumarshanti]

Hi,

I have designed the circuit & layout of an synchronous buck converter in 180nm technology (in Cadence). Now I am trying to implement the I/O pads around my core design. I do not have prior experience. Hence, please guide me the basics & the important considerations.
my converter output is 1V @ 100mA and input is 1.8V.

 

[erikl]

Try to get an I/O padLib for your process. Use several pads in parallel, if necessary.

 

[dick_freebird]

I think you should begin with considering what might go wrong,
or very wrong, with your converter. Inputs and outputs.

At the output, the negative undershoot on HL would likely
push a substrate current pulse into the part on every cycle
if you used the simple, standard Psub-N+ (or NW) diode as
a clamp. This could induce latchup at the I/O or interior if
you have not been perfectly diligent in guard-rings and
tried to get away with maximum "tap rule" distances / minimum
density. The substrate injection can also bother sensitive
analog behavior (reference, error amp, current comparators).
Even if you have a sync-buck output there may still be an
undershoot if there's any break-before-make period (and in
the name of efficiency, there had better). Whatever you use
for a clamp, you would like to ensure that its construction
keeps the current loop out of the substrate if possible.

At inputs, you can expect a lot if ground ringing and some
ESD schemes can rectify and charge-pump this ringing.
So your ESD stop siode might want to be two in series to
tolerate greater excursions without conducting (but of course
you do need to conduct at below BVox, and that is a bind
in lower voltage nodes). More series resistor than you think
necessary can take out a lot of the high frequency content
at the core. As a rule no input should be higher bandwidth
than it needs to be; there's nothing good attached to HF
signals in this application.

If you separate (say) power ground from analog ground,
those domains need to be cross-strapped effectively yet
benignly. One or the other (or neither) is going to be the
chip-scale ground - which, and have you asked the other
die occupants about their sensitivities and their induced
noise etc. (simultaneous switching in the digital sections
could bother you, as much as you bother them)?

In the interest of community relations, give some thought
about how you will wall off "your" piece of the substrate
from "theirs" against noise and minority carrier diffusion.