Mar 17, 2013 #1 T thussain Newbie level 4 Joined Jul 13, 2011 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,319 Dear All I am FPGA (VHDL) designer but for a specific project I need to compare my results with AT and TI controller. Kindly provide me Memory and I/O read/write (8/16 and 32 bit) data access latency for OMAP (4 or 5) and Atmel UC3 Micro-controllers. I am not familiar with OMAP and Atemel tool chains. Can we get average clock cycles for program while compile it on TI/Atmel SDKs. **broken link removed** regards,
Dear All I am FPGA (VHDL) designer but for a specific project I need to compare my results with AT and TI controller. Kindly provide me Memory and I/O read/write (8/16 and 32 bit) data access latency for OMAP (4 or 5) and Atmel UC3 Micro-controllers. I am not familiar with OMAP and Atemel tool chains. Can we get average clock cycles for program while compile it on TI/Atmel SDKs. **broken link removed** regards,