I need help VHDL 16 bit Parallel adder.

[wjswkvk208]

I made fullAdder.

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
	port(a, b, z : in  std_logic;
		 s, c : out std_logic);

end fulladder;

architecture dataflow of fulladder is
signal t1, t2, t3 : std_logic;
begin
	t1 <= a XOR b;
	t2 <= a AND b;
	s <= t1 XOR z;
	t3 <= t1 XOR z;
	c <= t2 OR t3;
end dataflow;

How to make 16 bit Parallel adder? plz get me a code..

 

[rajavel.rv]

these same architecture for 16-bit parallel adder also, u can write a code for structural modulation using portmap configuration of ur full adder to connect requirement of ur input and output.

Regards
rajavel.rv

 

[rca]

In vhdl, an adder is "+", two input vector of 16bits added together provides a 17bits output, you need to add saturation behind, that's it.