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I have problem with designing LDO.Please help!

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Newbie level 3
Aug 16, 2012
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Hanoi, Viet Nam
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i'm a newbie and i'm designing LDO with Vin=3.5 V and Vout=3.1 V. I have a problem that when i simulate with Vin increase from 0V to 3.5V.
If Vin increase from 0 to 3.5V in 5ms, vout is stably about 3.1 V.It's ok.(pic1).
But if Vin increase from 0 to 3.5V in shorter range of time, about 500us, vout is not stabe,it oscillate.(pic 2)
I asked some colleagues and they said that the reason is gain bandwidth of error amplifier is not high enough. It's correct or not ?
My professor required that this LDO must work well when the input voltage increase from 0 to 3.5 in 1us.
Can you give me some advices.
Thanks a lot

It seems that your bandwidth is not high not for such high transients. Are you sure that you have sufficient phase/gain margin?
Put the schematic and stability plots.

thank nitishn5.
I simulate loop gain and phase of LDO.PM is about 81 degree (pic 1).
And for Error amplifier,PM is about 76 degree.(pic 2).
I think PM is sufficient for stability.


My error opamp circuit used classical two stage op amp. I use 0.6 um library. It's difficult for me to increase the bandwidth to about 1Mhz.
Should i use another opamp's structure to take higher bandwidth ?
Give me some advices,please.

If you see the loop gain plot(pic 1) the phase curve starts from 180 degrees. This means that your phase at gain cross over is 180 + 81 degrees. Your LDO is unstable.
A two stage amplifier would have two poles and the pass transistor stage will have one pole. Unless your sizes are such that the poles are far apart, the architecture is unstable. Looking at your plots I don't think that you have used any compensation scheme.

Give the actual schematic.

Yes, thank you. My LDO is not stable.
I used two stage amplifier with a buffer at output to reduce the output resistance.
My EA's schematic is below

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