I have issues using a delay in VHDL

ggiacomo · Apr 22, 2018

Hello. I need to implement a certain block in VHDL. The design would be something similar to this one.

At first it seemed very easy to me, but after looking into it I realised I am not sure about how to handle the delay. The design has to be synthesizable, so I cannot use "after".
I have tried a simple approach but Im not sure if thats allowed. Assuming one clock cycle delay, the process is

Code VHDL - [expand]
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process(clk) is
begin
  if (clk'even and clk='1') then
    in_1_delayed<= in_1;
   end if;
end process;

Would it be the correct approach or there is a different way?

TrickyDicky · Apr 22, 2018

This is a 1 cycle delay (register). Except for the misspelling of event, it is the standard template.

FlyingDutch · Apr 23, 2018

Hello,

you can do it similary as in this example:

https://github.com/xesscorp/VHDL_Lib/blob/master/Delay.vhd

Regards

wtr · Apr 23, 2018

It's just semantics, but I'd recommend doing the following.

Code VHDL - [expand]
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if rising_edge(clk) then

I have issues using a delay in VHDL

ggiacomo

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TrickyDicky

Advanced Member level 7

ggiacomo

FlyingDutch

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wtr

Full Member level 5

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Code VHDL - [expand]
1 2 3 4 5 6	process(clk) is begin if (clk'even and clk='1') then in_1_delayed<= in_1; end if; end process;

I have issues using a delay in VHDL

ggiacomo

Newbie level 3

TrickyDicky

Advanced Member level 7

FlyingDutch

Advanced Member level 1

wtr

Full Member level 5

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