I have a question for design two frequency divide by 3 circuit in verilog !!

[pig8190]

1. Design two frequency divide-by-3 circuits, one with output div3a (33% duty cycle), the other with output div3b (50% duty cycle). You can use rising-edge and falling-edge FFs in your designs.
Write the verilog code to generate div3a and div3b and Write a test fixture???
Pls help me for that or give me some hint!!!!! Thank so much for help!!!!!!!!!!!!!