I can´t get this right

[Advark]

I have designed a operational transconductance amplifier, based en CMOS technology 0.35um. I want achieve a gm= 1mS. But at best case i only a gm between 0.3mS and 0.5mS.

M1 W=23.9u L=1u
M2 W=23.9u L=1u
M3 W=2.27u L=2u
M4 W=2.27u L=2u
M5 W=4.14u L=1u
M6 W=4.14u L=1u

 

[solidstate]

How about increasing the bias current?

And you swapped PMOS and NMOS labels?

 

[Advark]

I will try that, i don't swap the labels, What do you mean?

 

[Old Nick]

I will try that, i don't swap the labels, What do you mean?

The PMOS transistors should be connected to Vdd, not the NMOS.

M5 and M6 should be NMOS, the others PMOS

 

[Advark]

Yes, my bad.

M1,M2,M3,M4 are PMOS
m5,m6 are NMOS
Can you give an architecture when i can have a about 1mS o more for 0.35um CMOS.
And other thing where can i found a formula for gm that related the conductances of the mos transistor.

 

[edge_tv]

gm is not a thing of architecture, it is more about bias and sizing.So higher current -> higher gm, and higher W -> gm

 

[AdvaRes]

gm is not a thing of architecture, it is more about bias and sizing.So higher current -> higher gm, and higher W -> gm

I totaly Agree with you.
The key solution is transistor sizing.

 

[tdy]

I think the generation of I1 is important to get a good gm

 

[Humungus]

No other tourn around:
the Gm of the OTA is (gm/Id)1*I1/2

(gm/Id)1 could be at max 22, assuming you chose something like (gm/Id)1=10, then you need I1 at least 200uA.

No other possible solution. Please, go to the books.

 

[lylnk]

I agree with humngus.

The largest gm is limitted by Id.
I think the upper limit is 30*Id=15*I1. The pmos is in weak reversion mode now.