I am unable monitor early behavior of the design

[kovelapudi]

Hi,
I am working with chipscope pro analyzer to monitor my design signals. I have state machine in design. when i run the design in chipscope i am unable to see the initial states and behavior. I am unable to see where actually state transition is happening. some final settled state is showing. please help me how to test.

 

[aruipksni]

1/if your state are enumerated then you will need to built a .tok file with all you states.
2/ other option is that you don't have enought samples or you using the wrong clock to sample the state machine (slow clock).

 

[kovelapudi]

I am using sampling clock 3 times faster than the clock used for state machine

 

[TrickyDicky]

what are the issues - did you fully debug your design with a testbench?

 

[kovelapudi]

With testbench functionality is ok. Actually i wrote a state machine which switches its states depending on signals coming from associated modules in the design. depending on the signals the state machine has to reach the final state. In chipscope i am unable to monitor where these signals raising and falling. but state is reaching to final state.signal generation work with 3 times faster than state machine clock. I am using sampling clock as 3 times faster than the clock used in state machine in chipscope. I am unable to correlate the signals transition and state transition as they ought to be.

 

[aruipksni]

use same clock you are using for the sm. i.e synchronous.