i am designing high performance voltage controlled oscillator

[vlsi_vishal]

hello,
i am designing and simulate high performance voltage controlled oscillator but when i am writing the netlist have problem to get the Wmin and Lmin in 45nm technolohy in Hspice please tell me how can i select the minimum gate length and minimum gate width in 45nm technology in Hspice.

 

[Git]

Are you doing this for a learning project, or part of a commercial project?. If the latter, you are reinventing the wheel and may be better buying an off the shelf solution.

Git