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huffman compression method

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gkj

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Plz help me to write vhdl program for huffman compression method to compress 16bit
 

i have the following coding but while running this program i got xxxxx as output. i need the matrix calculation for huffman compression method in theoretical also.

Code: 
module nhj(CLK, RST, rdy_in, rl_in, dc_in,scan_type,
                   huffman_out);
						 output [15:0] huffman_out;     

input CLK, RST;
input [11:0] dc_in;
input rdy_in,scan_type;           
input[17:0] rl_in;   
/* signals */

reg cl_sum_rdy;
reg[3:0] size;
reg[5:0] cl_sum, cl_sum_prev;
reg[15:0] huffman_out;
reg[3:0] codelength_dc; 
reg[4:0] codelength_ac,codelength1,codelength2,codelength_ac1;
reg[9:0] vlcode_dc;
reg[17:0] vlcode1, vlcode2,vlcode3,vlcode4,vlcode_ac1,vlcode_ac;
reg full_flag1,half_flag1,half_flag2,full_flag2,half_flag3,full_flag3;
reg full_flag4,half_flag4,full_flag5,full_flag6,half_flag5;
reg[38:0] mult_out;
reg[16:1] upper_reg1,middle_reg1,lower_reg1,upper_reg2, middle_reg2, middle_reg3;
/*****************************************************************************/

always @ (posedge CLK)
    begin
	   casex (dc_in) 
         12'b111111111111 :  size = 4'd1;    
         12'b11111111110x :   size = 4'd2;     
         12'b1111111110xx :   size = 4'd3;     
         12'b111111110xxx :   size = 4'd4;     
         12'b11111110xxxx :   size = 4'd5;     
         12'b1111110xxxxx :   size = 4'd6;     
         12'b111110xxxxxx :   size = 4'd7;     
         12'b11110xxxxxxx :   size = 4'd8;     
         12'b1110xxxxxxxx :   size = 4'd9;     
         12'b110xxxxxxxxx :   size = 4'd10;     
         12'b10xxxxxxxxxx :   size = 4'd11;     
         12'b000000000000 :   size = 4'd0;     
         12'b000000000001 :   size = 4'd1;     
         12'b00000000001x :   size = 4'd2;     
         12'b0000000001xx :   size = 4'd3;     
         12'b000000001xxx :   size = 4'd4;     
         12'b00000001xxxx :   size = 4'd5;     
         12'b0000001xxxxx :   size = 4'd6;     
         12'b000001xxxxxx :   size = 4'd7;     
         12'b00001xxxxxxx :   size = 4'd8;     
         12'b0001xxxxxxxx :   size = 4'd9;     
         12'b001xxxxxxxxx :   size = 4'd10;   
         12'b01xxxxxxxxxx :  size = 4'd11; 
		 default: size = 4'd0;
         endcase
     end

	/******************** scan type = x, run = x, level = 1 ********/
always @ (posedge CLK)
begin
    casex ({scan_type,rl_in[17:12],rl_in[10:0]})

    {1'bx,6'bx,11'b00000000001}:
	    begin
        case({rl_in[17:12]})
		6'b010001:
		   begin  vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b010010: 
		   begin  vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b010011: 
		   begin  vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b010100: 
		   begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b010101: 
		   begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b010110: 
		   begin  vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd14; end
		6'b010111: 
		   begin  vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd14; end
		6'b011000: 
		   begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd14; end
		6'b011001: 
		   begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd14; end
		6'b011010: 
		   begin  vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd14; end
		6'b011011: 
		   begin  vlcode_ac1 <= {17'b00000000000011111,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b011100: 
		   begin  vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b011101: 
		   begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b011110: 
		   begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b011111: 
		   begin  vlcode_ac1 <= {17'b00000000000011011,rl_in[11]}; codelength_ac1 <= 5'd17; end
        endcase
		end
/******************** scan type = x, run = x, level = 2 ********/
    {1'bx,6'bx,11'b00000000010}: 
	    begin
        case({rl_in[17:12]}) 
		6'b000110: 
		   begin  vlcode_ac1 <= {17'b00000000000011110,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b000111: 
		   begin  vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b001000: 
		   begin  vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b001001: 
		   begin  vlcode_ac1 <= {17'b00000000000010001,rl_in[11]}; codelength_ac1 <= 5'd14; end
		6'b001010: 
		   begin  vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd14; end
		6'b001011: 
		   begin  vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b001100: 
		   begin  vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b001101: 
		   begin  vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b001110: 
		   begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b001111: 
		   begin  vlcode_ac1 <= {17'b00000000000010110,rl_in[11]}; codelength_ac1 <= 5'd17; end
		6'b010000: 
		   begin  vlcode_ac1 <= {17'b00000000000010101,rl_in[11]}; codelength_ac1 <= 5'd17; end
        endcase
		end		
	/******************** scan type = x, run = x, level = 3 ********/
    {1'bx,6'bx,11'b00000000011}: 
	    begin
        case ({rl_in[17:12]}) 
		6'b000011: 
		   begin  vlcode_ac1 <= {17'b00000000000011100,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b000100: 
		   begin  vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd13; end
		6'b000101: 
		   begin  vlcode_ac1 <= {17'b00000000000010010,rl_in[11]}; codelength_ac1 <= 5'd14; end
		6'b000110: 
		   begin  vlcode_ac1 <= {17'b00000000000010100,rl_in[11]}; codelength_ac1 <= 5'd17; end
        endcase
		end
	 /***************************************************************************************/

   {1'b1,6'bx,11'b00000000001}: 
	    begin
		case ({rl_in[17:12]}) 
		6'b000001 : 
		   begin  vlcode_ac1 <= {17'b00000000000000010,rl_in[11]}; codelength_ac1 <= 5'd4; end
		6'b000010 : 
		   begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd6; end
		6'b000011 : 
		   begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd6; end
		6'b000100 : 
		   begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd7; end
		6'b000101 : 
		   begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd7; end		
		6'b000110 : 
		   begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd8; end
		6'b000111 : 
		   begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd8; end
		6'b001000 : 
		   begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd8; end
		6'b001001 : 
		   begin  vlcode_ac1 <= {17'b00000000001111000,rl_in[11]}; codelength_ac1 <= 5'd8; end
		6'b001010 : 
		   begin  vlcode_ac1 <= {17'b00000000001111010,rl_in[11]}; codelength_ac1 <= 5'd8; end
		6'b001011 : 
		   begin  vlcode_ac1 <= {17'b00000000000100001,rl_in[11]}; codelength_ac1 <= 5'd9; end
		6'b001100 : 
		   begin  vlcode_ac1 <= {17'b00000000000100101,rl_in[11]}; codelength_ac1 <= 5'd9; end
		6'b001101 : 
		   begin  vlcode_ac1 <= {17'b00000000000100100,rl_in[11]}; codelength_ac1 <= 5'd9; end
		6'b001110 : 
		   begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd10; end
		6'b001111 : 
		   begin  vlcode_ac1 <= {17'b00000000000000111,rl_in[11]}; codelength_ac1 <= 5'd10; end		
		6'b010000 : 
		   begin  vlcode_ac1 <= {17'b00000000000001101,rl_in[11]}; codelength_ac1 <= 5'd11; end
        endcase
		end

 	/***************************************************************************************/

	{1'b0,6'b000000,11'bx}: 
	    begin
		case ({1'b0,rl_in[10:0]}) 
		12'b000000000010 : 
		   begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd5; end
		12'b000000000011 : 
		   begin  vlcode_ac1 <= {17'b00000000000000101,rl_in[11]}; codelength_ac1 <= 5'd6; end
		12'b000000000100 : 
		   begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd8; end
		12'b000000000101 : 
		   begin  vlcode_ac1 <= {17'b00000000000100110,rl_in[11]}; codelength_ac1 <= 5'd9; end
		12'b000000000110 : 
		   begin  vlcode_ac1 <= {17'b00000000000100001,rl_in[11]}; codelength_ac1 <= 5'd9; end
		12'b000000000111 : 
		   begin  vlcode_ac1 <= {17'b00000000000001010,rl_in[11]}; codelength_ac1 <= 5'd11; end
		12'b000000001000 : 
		   begin  vlcode_ac1 <= {17'b00000000000011101,rl_in[11]}; codelength_ac1 <= 5'd13; end
		12'b000000001001 : 
		   begin  vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd13; end
		12'b000000001010 : 
		   begin  vlcode_ac1 <= {17'b00000000000010011,rl_in[11]}; codelength_ac1 <= 5'd13; end	
		12'b000000001011 : 
		   begin  vlcode_ac1 <= {17'b00000000000010000,rl_in[11]}; codelength_ac1 <= 5'd13; end
		12'b000000001100 : 
		   begin  vlcode_ac1 <= {17'b00000000000011010,rl_in[11]}; codelength_ac1 <= 5'd14; end
		12'b000000001101 : 
		   begin  vlcode_ac1 <= {17'b00000000000011001,rl_in[11]}; codelength_ac1 <= 5'd14; end
		12'b000000001110 : 
		   begin  vlcode_ac1 <= {17'b00000000000011000,rl_in[11]}; codelength_ac1 <= 5'd14; end
		12'b000000001111 : 
		   begin  vlcode_ac1 <= {17'b00000000000010111,rl_in[11]}; codelength_ac1 <= 5'd14; end
		endcase
		end

 /***************************************************************************************/

	{1'b0,6'bx,11'b00000000010}: 
	    begin
		case ({1'b0,rl_in[10:0]})
		12'b000000000001 : 
		   begin  vlcode_ac1 <= {17'b00000000000000110,rl_in[11]}; codelength_ac1 <= 5'd7; end
		12'b000000000010 : 
		   begin  vlcode_ac1 <= {17'b00000000000000100,rl_in[11]}; codelength_ac1 <= 5'd8; end
		12'b000000000011 : 
		   begin  vlcode_ac1 <= {17'b00000000000100100,rl_in[11]}; codelength_ac1 <= 5'd9; end
		12'b000000000100 : 
		   begin  vlcode_ac1 <= {17'b00000000000001111,rl_in[11]}; codelength_ac1 <= 5'd11; end
		12'b000000000101 : 
		   begin  vlcode_ac1 <= {17'b00000000000001001,rl_in[11]}; codelength_ac1 <= 5'd11; end
        endcase
		end
endcase
end
/*****************************************************************************/

always @ (posedge CLK)
  if (RST)
     begin 
      vlcode_ac <= {18'b0}; 
		codelength_ac <= 5'd0;
     end
  else if (vlcode_ac <= vlcode_ac1) 
		begin
		 codelength_ac <= codelength_ac1; 
 		 end
   else if (rdy_in == 1'b1)
       begin
	     codelength2 <= codelength1; 
       vlcode2 <= vlcode1; vlcode3 <= vlcode2;vlcode4 <= vlcode3;
       end
   
/*****************************************************************************/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       cl_sum <= 6'b100111; cl_sum_prev <= 6'b0;
       half_flag1 <= 1'b0; full_flag1 <= 1'b0;
       end
   else if ( cl_sum_rdy == 1'b1)
       begin
          if (cl_sum_prev < 6'd16)
            begin  
            cl_sum_prev <= codelength1 + cl_sum_prev;
            cl_sum <= (6'b100111 - cl_sum_prev);
            half_flag1 <= 1'b0;
            full_flag1 <= 1'b0;
			     end
          else if (cl_sum_prev <= 6'd32 && cl_sum_prev >= 6'd16)
            begin 
            cl_sum_prev <= codelength1 + (cl_sum_prev - 5'b10000);
            cl_sum <= (6'b100111 - cl_sum_prev);
            half_flag1 <= 1'b1;
            full_flag1 <= 1'b0;
			     end
          else if (cl_sum_prev >= 6'd32)
            begin 
            cl_sum_prev <= codelength1 + (cl_sum_prev - 6'b100000);
            cl_sum <= (6'b100111 - cl_sum_prev);
            half_flag1 <= 1'b1;
            full_flag1 <= 1'b1;
			     end
       end
   end

/*****************************************************************************/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       mult_out <= 39'b0; 
       full_flag2 <= 1'b0; half_flag2 <= 1'b0;
       full_flag3 <= 1'b0; half_flag3 <= 1'b0;
       full_flag4 <= 1'b0; half_flag4 <= 1'b0;
       full_flag5 <= 1'b0; half_flag5 <= 1'b0;
       full_flag6 <= 1'b0;
       end
   else if (rdy_in == 1'b1)
       begin
         mult_out <= vlcode4 * vlcode4;
         full_flag2 <= full_flag1; half_flag2 <= half_flag1;
         full_flag3 <= full_flag2; half_flag3 <= half_flag2;
         full_flag4 <= full_flag3; half_flag4 <= half_flag3;
         full_flag5 <= full_flag4; half_flag5 <= half_flag4;
         full_flag6 <= full_flag5; 
       end
end

/*****************************************************************************/
always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       upper_reg1 <= 16'b0; middle_reg1 <= 16'b0; lower_reg1 <= 16'b0;
       end
   else if (rdy_in == 1'b1)
       begin
         case({full_flag4, half_flag4})
         2'b00: begin upper_reg1[16:1] <= mult_out[38:23] | upper_reg1[16:1];
                      middle_reg1 <= mult_out[22:7] ;
                      lower_reg1 <= {mult_out[6:0],9'b0 }; end
         2'b01: begin upper_reg1[16:1] <= mult_out[38:23] | middle_reg1[16:1];
                      middle_reg1 <= mult_out[22:7];
                      lower_reg1 <= {mult_out[6:0],9'b0}; end
         2'b11: begin upper_reg1 <= mult_out[38:23] | lower_reg1;
                      middle_reg1 <= mult_out[22:7];
                      lower_reg1 <= {16'b0}; end
         default:begin upper_reg1 <= upper_reg1;
                      middle_reg1 <= middle_reg1;
                      lower_reg1 <= lower_reg1; end
         endcase
       end     
   end

/*****************************************************************************/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       upper_reg2 <= 16'b0; middle_reg2 <= 16'b0; 
       middle_reg3 <= 16'b0; 
       end
   else if (rdy_in == 1'b1)
       begin
          upper_reg2 <= upper_reg1;
          middle_reg2 <= middle_reg1;
          middle_reg3 <= middle_reg2;
          
       end     
   end

/*****************************************************************************/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       huffman_out <= 16'b0; 
       end
   else if (rdy_in == 1'b1)
       begin
       if (half_flag5 == 1'b1)
           huffman_out <= upper_reg2;
       else if (full_flag6 == 1'b1)
           huffman_out <= middle_reg3;
			end
    end

endmodule
 
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