Hspice simulation program

[illiviu]

I am simulating a chain of IO module for ground bounce characterisation. These modules are identic. With two or three modules simulation is working, but for more not. Error mesages are:

- "internal timestep too small in transient analysis"
I changed some .OPTIONS statement, but it 's useless

- "values of the gate oxide cap, cox are too small. Calculated value is Cox=0.000
Please check your model"

- some " warning parameter em<5.0e5 invalid. Set defaults em=4.1e7 to run"

In models default value is em=0, but I think is a minor problem.

These errors do not appear simultaneously, but only when number of modules is increasing .

Modules are identical and conected identical. Netlist is generated by a schematic program and is correct.
I don't know if it's a model or simulator problem. I am using ST 0.13 libraries .

Does anybody know a solution ?

 

[Humungus]

The problem concerning your timestep arises from the tries the simulator does to converge. As he tries a lot, each iteration reducing the timestep, somewhere the time step becomes smaller than the minimum accepted value. Just set parameter (I think) HMIN enough small as to avoid this kind of errors.

 

[illiviu]

There is not such a parameter HMIN. Maybe GMIN or RMIN. I will try with both of them.

 

[Hughes]

In addition, you may try to use a SMALL timestep value in .TRAN statement.

 

[illiviu]

I tried to change timestep, I tried some another .OPTIONS. Still not work.

But I maded a simulation with some TSMC models and it's working. Maybe ST models are too complex ? They used transistor modelling as .subckt type, with a base model and internal equations that are changing some parameters.
What can be wrong ?

 

[yorande]

I think it's just that complex model with subcircuit is much easier to get no convergence.
Maybe you need to get some idea of the subcircuits and see your circuit topology for that.

 

[illiviu]

Simulation still not work with HSPICE. But the same circuitis is working with HSIM, without problems and very quickly.
Maybe is a HSPICE bug ? I am using version 2003.6

 

[ablue]

You can try to set .option itl4 = 50 or more , default itl4 = 8 .
Spice will decrease its timestep to 1/8 of original timestep when the iteration reaches itl4. also if the timestep is small then the minimum step , then "internal timestep too small in transient analysis". so if you set itl4 larger , simulator will have more chances to converge instead of decrease the timestep.
Wish it can work

ablue

 

[nkchenliy]

I think this is a problem about convergence of spice.

 

[nafaiz]

here i attached a simulation guide for hspice....maybe it may help u....

this is hspice tutorial book



and here are some links about hspice manual





and this is the link to another hspice book

 

[itaifrenkel]

illiviu ,

Ansoft has recognized this problem a few years ago, and they developed an HSPICE compatible simulator that can solve much bigger netlists, and has improved convergence.

See the goolge search below:

https://www.google.com/search?hl=en&q=nexxim

Itai

 

[layes2]

perhaps you need a initial condition

 

[bg21359]

- "internal timestep too small in transient analysis"

This looks like spice convergence problem. It's not a bug, just how the numerical method works for non-linear circuitry. You need to check hspice manual and find out which options you need to change in order to change RELTOL, ABSTOL/VNTOL, ITL4.
Or add initial conditions for some important nodes. At last, maybe your model is not good, not smooth for some important parameters.

 

[nullein]

Maybe, it is convergence problem....

 

[chenliy]

bg21359 is right. "internal timestep too small in transient analysis" is a complex problem. You can see the book "The Designer's guide to SPICE and Spectre" by K. S. Kundert. It will help you.

 

[leonken]

illiviu ,

Ansoft has recognized this problem a few years ago, and they developed an HSPICE compatible simulator that can solve much bigger netlists, and has improved convergence.

See the goolge search below:

h**p://www.google.com/search?hl=en&q=nexxim

Itai

Where can i download the nexxim?

 

[markty]

Try a smaller step in your tran analysis. It may help.

or you can use hsim to generate a .ic volts and run hspice with initial values, because hspice is more accurate.

 

[leonken]

when I do circuit design I also encounted such problem.
One of solutions is maybe the principle of your circuit indeed exits some problems.

 

[newhand]

hi:
I have encountered such problems before,it is the simulator u use that is not able to converge in your circuit.Converage problems occur most when there is a feedback loop in your circuit and my suggestion is as belows:
1. Modify the timestep of your tran analysis as small as possible balancing between the simulation speed and converage.
2. Connect a capacitor to ground which is in the order of fF at the node of your feedback loop which your think may great affect your circuit statement.
3. Use a pwl power supple so that when we simulate the circuit,we can get a slow start and it can prevent unconverage.

hope it help~~

 

[layes2]

may rel-2 help