Solutions for transient convergence
The following solutions apply to problems with transient convergence:
Solution 0. Check circuit topology and connectivity (as in solution 0 in the dc analysis).
Solution 1. Set RELTOL=.01 in the .OPTIONS statement. For example, specify ".OPTIONS RELTOL=.01." For most simulations, reducing RELTOL speeds simulation 10 to 50% with only a minor loss in accuracy. You can set RELTOL to .01 for initial simulations and then reset it when you have the simulation going the way you like it and need a more accurate answer.
Solution 2. Set ITL4=100 in the .OPTIONS statement. For example, specifying ".OPTIONS ITL4=100'' increases the number of transient iterations at each time point that IsSpice goes through before giving up.
Solution 3. Reduce the accuracy of ABSTOL and VNTOL if current and voltage levels allow. For example, specify ".OPTIONS ABSTOL=1N VNTOL=1M." You can set ABSTOL and VNTOL about eight orders of magnitude below the average voltage and current. Defaults are "ABSTOL=1PA" and "VNTOL=1UV."
Solution 4. Model your circuit realistically. Add parasitics, especially stray and junction capacitance. The idea here is to smooth any strong nonlinearities or discontinuities, which you can do by adding capacitance to various nodes and by making sure that all semiconductor junctions have capacitance. Other tips include:
* Use RC snubbers around diodes.
* Specify capacitance for all semiconductor junctions (3 pF for diodes, 5 pF for BJTs if you do not know the specific value).
* Add realistic circuit and element parasitics.
* Find a subcircuit representation if the model doesn't fit the device behavior, especially for RF and power devices like RF BJTs and power MOSFETs.
Many vendors cheat by trying to "force-fit" the Spice .MODEL statement to represent a device's behavior. This is a sure sign that the vendor has skimped on quality in favor of quantity. You cannot use primitive .MODEL statements to model most devices above 200 MHz because of the effects of package parasitics, and you cannot use .MODEL statements to model most power devices because of extreme nonlinear behavior. In particular, if your vendor uses a .MODEL statement to model a power MOSFET, throw away the model. It's almost certainly useless for transient analysis.
Solution 5. Reduce the rise and fall times of PULSE sources. For example, change "VCC 1 0 PULSE 0 1 0 0 0'' to "VCC 1 0 PULSE 0 1 0 1U 1U." Again the point is to smooth strong nonlinearities. Pulse times should be realistic, not ideal. If you don't specify rise or fall times or if you specify 0, the times default to the TSTEP value in the .TRAN statement.
Solution 6. Change to gear integration. For example, specify ".OPTIONS METHOD=GEAR." You should couple gear integration with a reduction in the RELTOL value. This technique tends to produce a more stable numerical solution, while trapezoidal integration tends to produce a less stable solution. Gear integration often produces superior results for power circuitry simulations because of the high-frequency ringing and long simulation periods gear integration involves. IsSpice includes both trapezoidal and gear integration.
Special casesYou can take additional steps in some cases. With MOSFETs, check the connectivity; connecting two gates to each other but to nothing else results in a PIVTOL or singular-matrix error. Also check the model level. Spice 2 does not behave properly when MOSFETs of different levels are in the same simulation.
For long transient runs, set .OPTIONS parameter ITL5 to 0 to specify that the simulation run to completion, no matter how many iterations it takes. For good reason, Spice 3 eliminates the need for both the ITL5 and LIMPTS options.