*Single CMOS Schimitt trigger circuit
.INCLUDE '/home/icsrl/TECHNOLOGY/FROM_MOSIS/TSMC/65nm/PDK/CRN65GP/models/hspice/crn65gplus_2d5_lk_v1d0.l'
.LIB '/home/icsrl/TECHNOLOGY/FROM_MOSIS/TSMC/65nm/PDK/CRN65GP/models/hspice/crn65gplus_2d5_lk_v1d0.l' MOS
vdd 6 0 DC 1V
vin 2 0 PULSE (0 1 0n 0.4n 0.4n 14.6n 30n)
*Schimitt trigger circuit
mp1 5 4 6 6 pch.1 W=15u L=10u
mp2 3 2 5 6 pch.1 W=15u L=10u
mp3 4 3 5 6 pch.1 W=15u L=10u
mn1 1 4 0 0 nch.1 W=10u L=10u
mn2 3 2 1 0 nch.1 W=10u L=10u
mn3 4 3 1 0 nch.1 W=10u L=10u
.TRAN 0.01ns 60ns
.PROBE post=1
.END