i try to design one rail to rail MOS op-amp
i use orcad for plot the circuit and then by R&H convert to hspice model my AC design have no out put and in .sp file of hspice i see
**diagnostic** dc convergence failure,
resetting dcon option to 1 and retrying
**diagnostic** dc convergence successful
you can increase the efficiency of the
operating point calculation by setting dcon= 1
in the .option statement
is my problem for this massage ?
Your error message suggests that the simulation results did converge which would suggest that isn't the problem. However, the fact that the simulation is struggling to converge could mean you have a floating node and hence a drawing mistake or circuit design error.
It would be useful to have a circuit but I have stripped out the superfluous bits in the list file and removed the sfvtflag = 0 from the models (my simulator doesn't seem to like that) and it simulates OK. VOUT is a gain of 50dB with a UGB of 171MHz. Is that what you were expecting?
How did you simulate it?
This output is not really what i need.I need gain of 80dB and UGB of 200M
but if my design reach to this result is really good for me and i can improve my result .My more important problem is that i cannot see any out put for my design.
I use SIMetrix. I simply used you list file and stripped out the superfluous stuff so I was left with the models, netlist & AC command. What do you get when you simulate? Zero gain? It would seem strange that running the same netlist on two simulators produces different results. Are you sure you are probing the output correctly? I probed VOUT.
What do you mean by "nothing"? Have you looked at various nodes within the circuit? Have you looked at the DC operating point? You still haven't posted a circuit diagram.
It is clear that the netlist is OK - I got some sensible results from it. So, that would suggest there is something wrong with how you are probing the circuit to view the results.