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Hspice calculation of delay and leakage and dynamic power of d flipflop

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Upadhyay Prachi

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i have written a hspice code for d flipflop and i want to calculate the delay of the circuit i.e. high to low and low to high propagation delay but my code is running but not able to give the values of delay


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* dff.sp
***********dff*******************8888
* Parameters and models
 
*------------------------------------------------
.param SUPPLY=1.8
.option scale=45n
.include c:/users/prachi/desktop/models.sp
.option post ruvnl=5
* Simulation netlist
*------------------------------------------------
Vdd vdd gnd 'SUPPLY'
Vin1 d gnd PULSE 0 'SUPPLY' 2ps 0ps 0ps 100ps 200ps
Vin2 en gnd PULSE 0 'SUPPLY' 15ps 0ps 0ps 100ps 200ps
Vin3 clk gnd PULSE 0 'SUPPLY' 35ps 0ps 0ps 100ps 200ps
**************1***************************
Mp25 enbar en vdd vdd pmos1 W=4 L=1
Mn25 enbar en gnd gnd nmos1 W=2 L=1
****************invert of enable that is enbar **********************
******************************************
Mp26 o12 d 0 vdd pmos1 W=4 L=1
Mp27 o12 en 0 vdd pmos1 W=4 L=1
Mn26 o12 d b12  gnd nmos1 W=2 L=1
Mn27 b12 en vdd  gnd nmos1 W=2 L=1
******************input of and gate d and en and output o12********************88
********************************
Mp28 o13 enbar 0 vdd pmos1 W=4 L=1
Mp29 o13  o18  0 vdd pmos1 W=4 L=1
Mn28 o13 enbar b13  gnd nmos1 W=2 L=1
Mn29 b13 o18 vdd  gnd nmos1 W=2 L=1
c1 013
 
******************input of and gate o18 and enbar and output o13********************88
********************************
Mp30 b14 o12 0 vdd pmos1 W=4 L=1
Mp31 o14 o13 b14 vdd pmos1 W=4 L=1
Mn30 o14 o13 vdd gnd nmos1 W=2 L=1
Mn31 o14 o14 vdd gnd nmos1 W=2 L=1
 
Mp1 b a1 0 vdd pmos1 W=4 L=1
Mp2 o1 a2 b vdd pmos1 W=4 L=1
Mn1 o1 a1 vdd gnd nmos1 W=2 L=1
Mn2 o1 a2 vdd gnd nmos1 W=2 L=1
*********or gate with input o13 and o12 and output o14***************
 
Mp32 o15 o14 vdd vdd pmos1 W=4 L=1
Mn32 o15 o14 gnd gnd nmos1 W=2 L=1
 
****************invert of o14 that is o15 **********************
******************************************
Mp33 o16 o14 vdd vdd pmos1 W=4 L=1
Mp34 o16  clk vdd  vdd pmos1 W=4 L=1
Mn33 o16 o14 b15  gnd nmos1 W=2 L=1
Mn34 b15 clk gnd  gnd nmos1 W=2 L=1
 
******************input of nand gate o14 and clk and output o16********************88
********************************
Mp35 o17 o15 vdd vdd pmos1 W=4 L=1
Mp36 o17  clk vdd vdd pmos1 W=4 L=1
Mn35 o17 o15 b16  gnd nmos1 W=2 L=1
Mn36 b16 clk gnd  gnd nmos1 W=2 L=1
 
******************input of nand gate o15 and clk and output o17********************88
********************************
Mp37 o18 o16 vdd vdd pmos1 W=4 L=1
Mp38 o18  o19 vdd vdd pmos1 W=4 L=1
Mn37 o18 o16 b17  gnd nmos1 W=2 L=1
Mn38 b17 o19 gnd  gnd nmos1 W=2 L=1
 
******************input of nand gate o16 and o19 and output o18 final output********************88
********************************
Mp39 o19 o17 vdd vdd pmos1 W=4 L=1
Mp40 o19  o18 vdd vdd pmos1 W=4 L=1
Mn39 o19 o17 b18  gnd nmos1 W=2 L=1
Mn40 b18 o18 gnd  gnd nmos1 W=2 L=1
 
******************input of nand gate o17 and o18 and output o19********************88
********************************
 
*------------------------------------------------
.tran 1ps 200ps
.measure tpdr * rising prop delay
+ TRIG v(d) VAL=0.9 FALL=1
+ TARG v(o18) VAL=0.9 RISE=1
.measure tpdf * falling prop delay
+ TRIG v(d) VAL=0.9 RISE=1
+ TARG v(o18) VAL=0.9 FALL=1
.measure tpd param='(tpdr+tpdf)*0.5' * average prop delay
*******************
.probe  v(d) v(o18)
.end



please anybody tell me what is the problem behind it
 
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