howto determine the FIFO Depth

[arunapai]

fifo design

Hi All,

I have a design issue, I have an interface between two domains:

Input is a 16 bit parallel data at 500MHz

Output is 1 bit serial data at 50 MHz,

I need to maintain my throughput at 500Mbps.

For this scenario, I need to design a FIFO.

Can anyone help me with the FIFO design, especially the FIFO depth?

Thanks,
Arun

 

[shanmugaveld]

FIFO Depth

Check this link..
Hope it will help you to decide FIFO Depth..

**broken link removed**

 

[arunapai]

Re: FIFO Depth

Thanks,

The concept was clear, but I am not able to related it to my design issue.

Can u pls work out the FIFO depth for me?

 

[syncom]

FIFO Depth

Output is 1 bit serial data at 50 MHz,

I need to maintain my throughput at 500Mbps?
May you explain it more detail ?

 

[penrico]

Re: FIFO Depth

arunapai,

In this scenario, your FIFO can't work.

Always the output must be faster than input. If not, FIFO will be fulled and then lost data.

500Mhz x 16 bit = 8000 Mbps at input. And you have 50 Mbps at output.

FIFO is only for temporally stops in output channel. Not for lowest speed output.

 

[palai_santosh]

FIFO Depth

"I need to maintain my throughput at 500Mbps
Output is 1 bit serial data at 50 MHz,"

cosidering this two statements
FiFo output width is 1 and clock is 500Mhz.

"Input is a 16 bit parallel data at 500MHz "
this is not fully explained.
could be two cases
1. Continuous flow of data????? Answer is very bad . you can't have a fifo working here..

2. 16 bit parallel data at a clock of 50Mhz but in burst mode. and throughput of data is 500Mbps/slower.

then you can have the fifo with full or programmable full signals. and use the ref. given by "shanmugaveld" to calculate the depth.

hope it helps.

 

[teja321]

FIFO Depth

Lets consider the other way around.
Input is 1 bit; clock is 500 Mhz.
Output is 16 bit ; clocked at 50 Mhz.

what should be the fifo depth?

 

[ashiram]

Re: FIFO Depth

Here is the answer.

input 500Mhz 16 bit
Output 50 Mhz 1 bit
Let us consider 500/50 = 10 .

That means 10 clocks of input write, we can only have one clock of output read.
in 10 clocks, How many data it can able to write = 10*16 = 160 bits.
In read side, we have only one clock. It can able to read = 1 bit.
FIFO Depth = 159.
But clocks are asynchronous, we can round upto = 160/
FIFO Depth 160
-RAM

 

[omara007]

Re: FIFO Depth

Here is the answer.

input 500Mhz 16 bit
Output 50 Mhz 1 bit
Let us consider 500/50 = 10 .

That means 10 clocks of input write, we can only have one clock of output read.
in 10 clocks, How many data it can able to write = 10*16 = 160 bits.
In read side, we have only one clock. It can able to read = 1 bit.
FIFO Depth = 159.
But clocks are asynchronous, we can round upto = 160/
FIFO Depth 160
-RAM

No, this is not correct .. If input is faster than the output and there is no silence interval, the FIFO can't be a solution.

Suppose you insisted on using a FIFO of depth 160 bit. What happens after the first time it gets filled ? .. I will tell you:
1. At the output, only one bit is read and the FIFO occupation becomes 159bit and only one bit becomes available for the next 16-bit to be written .. this means that the data at the input won't find a room to be written to.
2. If you want to operate a FIFO here, then you need to have a silence interval to let the FIFO gets empty before you fill it again.