How was the verilog-A language simulated ?

[Muthuraja.M]

Hi friends,

Verilog HDL is simulated by modelsim and synthesized by xilinx.

Is verilog-A language is simulated using modelsim ?

If no which software is used to simulate the verilog-A language ?

Reply me.


Thanks in advance...

 

[dave_59]

Questa-ADMS can simulate Verilog-A. It is an extension to Modelsim.

 

[Muthuraja.M]

ok fine.

i am having modelsim 6.3gp1 version. By using this can we simulate the verilog-A language.

 

[dave_59]

No, you need Questa-ADMS

https://www.mentor.com/products/ic_nanometer_design/analog-mixed-signal-verification/eldo/

 

[Muthuraja.M]

Is there is any student version for Questa ADMS to download...