How venders will define the values of setup & hold?

[sathi.repala]

Hello,

can any one explain how venders will define the values of SETUP & HOLD.
i mean on which basis?

 

[oratie]

They simulate their transistor-level curcuits (flip-flop) in spice simulator, and see for different values of setup/hold if circuit fails or not (data from input passed to output or not).

 

[sathi.repala]

They simulate their transistor-level curcuits (flip-flop) in spice simulator, and see for different values of setup/hold if circuit fails or not (data from input passed to output or not).

Hi oratie,
Thank u......


i heard that after fabrication of test chip the setup/hold values are extracted practically. is it true...
and one more question that if the circuit passes for different values, which one will be considerable...

 

[mvtejas]

Hi,

I think, it is both ways. Designers first do the transistor level simulations of their libraries and then compare it with test-chip results to factor in some variation and other stuff.

So, I think to answer your question, it is both.

HTH,
-Tejas

 

[ayush717]

Hi ..
Just to add to the above, first when a request for a new technology-node arrives from a customer, the standard-cell library is designed and characterized on CAD for different operating condition ( depending upon the usage/application ). This characterization is "mostly" spice-simulation. Once first set of library is ready, it is further fabricated on silicon through test-chips and parameters are estimated(through dedicated circuits). On the basis of correlation between the CAD value and silicon value, the library is certified to be used in any pilot-project/product.

Correct me if I am wrong.

Cheers,