how to write ucf file in xilinx for vhdl code for an std_logic_vector

[jincyjohnson]

How can we write a ucf file in xilinx. I want to take 8 bit patterns as output. There are 16 such patterns. In each clock one 8 bit pattern is given to output. How an std_logic_vector can be coded in an ucf file. plz reply

 

[barry]

UCF files are for constraints. I really have no idea what you are trying to do. Are you trying to, perhaps, generate a TESTBENCH? What do you mean by 'coding' a std_logic_vector in a file?

 

[jincyjohnson]

In my coding, I generate some patterns. Each pattern is of 8 bit . There are 16 such patterns. I want to take these patterns as output. So output is an std_logic_vector. (outputut std_logic_vector(7 downto 0)).How the ucf code caan be written

 

[barry]

You're not paying attention. A UCF file is for constraints.

Ok, so your code generates 8-bit std_logic_vectors. What do you mean "I want to take these patterns as output"?

 

[imbichie]

UCF means User Constraints File.
It contains all the IO ports list with its PIN number of the Specified FPGA.
And the type of IO pin Package like LVCMOS, LVDS, LVTTL, etc..
It also contains the clock Constraints like the frequency of the clock and the setup and hold time Constraints etc,
All these clock Constraints are depends on your design.
All these Constraints are written by specified a syntax given by the FPGA vendor.
Other than this there is no coding for the UCF file.
This File is used at the time of design synthesis.
For testing/verification the design there is no need of UCF file

 

[rajavel.rv]

In my coding, I generate some patterns. Each pattern is of 8 bit . There are 16 such patterns. I want to take these patterns as output. So output is an std_logic_vector. (outputut std_logic_vector(7 downto 0)).How the ucf code caan be written

Hi ur question is how to write a ucf for std_logic_vector of 8 bit; u can declare that same for single pin assignment but ur identify which bit ur declared;
ex:

output : out std_logic_vector(7 downto 0);

NET "output[7]" LOC = "A15" | SLEW = FAST;
NET "output[6]" LOC = "A15" | SLEW = FAST;
NET "output[5]" LOC = "A15" | SLEW = FAST;
NET "output[4]" LOC = "A15" | SLEW = FAST;
NET "output[3]" LOC = "A15" | SLEW = FAST;
NET "output[2]" LOC = "A15" | SLEW = FAST;
NET "output[1]" LOC = "A15" | SLEW = FAST;
NET "output[0]" LOC = "A15" | SLEW = FAST;


Regards
rajavel.rv