can any one uplaod how to write testbenches for functional verification of hdl code for beginners. any site for beginners or any pdf books for learning ......
I think if u know how to write a code u can write the test bench easily.
Or,
In a simplistic manner for very small ckts. u can just put the different input values at different times by invoking the actual design in ur test bench but it is not the good way.
I suggest u to generate a random number generator for that
I'm soon launching a Verification training in Bangalore to take a comprehensive look at this topic, not for free (as I spend several hours putting together the material). If interested see: www.noveldv.com and/or write to: ajeetha <> gmail.com
Regards
Ajeetha, CVC www.noveldv.com
Ajeetha Kumari
* New Book: A Pragmatic Approach to VMM Adoption
* SystemVerilog Assertions Handbook,
* Using PSL/SUGAR
Design Verification Consultant,
Contemporary Verification Consultants Private Limited,
Bangalore, India, http://www.noveldv.com
can any one uplaod how to write testbenches for functional verification of hdl code for beginners. any site for beginners or any pdf books for learning ......