Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to write data of the bus in a text file using verilog

Status
Not open for further replies.

pankaj jha

Full Member level 3
Joined
Apr 16, 2010
Messages
170
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Location
jaipur
Activity points
2,457
Hi all,
I am running a AMS simulation in Cadence virtuoso. My output from a block (in verilog code) is a bus of 19 bits.
I want to write a verilogA code to write the bus data (at every negative edge of clock) in a text file.

Can anyone help me with the code???
 

longtv8

Newbie level 1
Joined
Apr 25, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
6
Hi Pankaj jha.

i hope this is code you need

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
integer file_open;
initial begin
      // Open file 
      file_open = $fopen("bus19.txt", "w");
end
 
always @(negedge clk) begin 
    if(flag_latch_bus_out)
        $fwrite(file_open, "%h\n",bus_name);// bus_name: you want to get values.// %h you want to write bus data is hex / %d : decimal
end

 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top