Re: how to write a rising-edge D flip flop program using a Verilog
I found it - I had accidentally added something from a comment block in as code and that is what the issue was. I removed it and then it complied successfully.
I found it - I had accidentally added something from a comment block in as code and that is what the issue was. I removed it and then it complied successfully.
that's good. but... now think about the task at hand. describing a flip-flop module is not what RTL is supposed to be used for. you want to write code that will infer a flop. it's a subtle but important difference.