Hi,
I want to write into the memory through a port and sometimes after I have it read the memory content through the same port. How to do this? I am unfamiliar about inout port
I2C uses inout to implement the open drain buffers. In standard I2C, the bus lines are either driven 0 or z, never 1.
In hardware terms, a tri-state buffer is the equivalent of an inout. Bidirectional data busses, e.g. memory data lines need to use tri-state buffers at all connected ports.
I'll assume that the mixed case keywords is also an artifact of using the phone.
Code Verilog - [expand]
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Input[3:0] data,//has to be a typo too, because this won't compile?Outputreg[3:0]);
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This piece of code doesn't make a whole lot of sense:
Code Verilog - [expand]
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always@(posedge clkb)If(re)
Temp<= ram[addrb];Assign data = re ? Temp: 'dz;
when a re pulses high for one clock cycle and is caught on the rising_edge of clock it will have gone away in the next cycle when the temp is assigned to data (in reality it will likely stick around for a few hundered ps due to Tco and routing delays). Only if re is high for two clock cycles with this work correctly, i.e. 1st clock reads the ram 2nd clock outputs the data. To properly enable the output you would have to use a delayed version of the re.