how to verify input and output of FFT ip from logicore Xilinx library

[Izhar Ahmed]

how to verify input and output of FFT ip from logicore Xilinx library and why it is not synthesizable and how to use chipscope analyzer and is there any need of digilink cable for it

 

[barry]

1) Put a known signal in and see if you get the proper output.
2) It most certainly is synthesizable.
3) What do you mean "how to use chipscope"? Do you have a specific question, or are you asking for a tutorial instead of reading the manual?
4) A digilink cable, as far as I know, is for some kind of network connection. I have no idea how it applies to your situation. You need the Xilinx JTAG cable in order to use chipscope, if that's what your're asking.

 

[ads-ee]

I think the OP meant a Digilent cable, I think that Digilent's cable works with Chipscope as I believe others on this forum have used it. I've never used one as I've always had a Xilinx cable around.

The FFT is synthesizable if you have the RTL/encrypted_RTL otherwise it's probably in the form of a Xilinx proprietary binary netlist. Never used it so I don't know what Coregen produces. It should be pretty obvious if you create the core to look in the core's directory and see what coregen produces.

 

[Izhar Ahmed]

which simulation tool are you using

 

[Izhar Ahmed]

ok sir i understand that i need jtag cable ok with that
when we run xilinx logicore library it gives us output model sim as waveform where should i put inputs from where should verify output as i am new to this field i am unable to understand how to verify it

 

[barry]

Logiccore will give you a VHDL or Verilog output file. You instantiate it into your design just like you would any other component.