during netlist simulation with SDF, all timing checks are enabled for all FFs except for the 1st FF of the synchronizer (VCS has this feature)
the goal is to check if the data bus crossing do not violate setup/hold timing (i.e. the synchronized control signal properly gates the data to the destination clock domain, and that the data does not change while the synchronized signal is asserted)
the test needs to be ran multiple times. each iteration has a different skew/shift between the 2 clocks