Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to verify a 32-bit full adder with testbench

Status
Not open for further replies.

rfsystem

Advanced Member level 3
Joined
Feb 25, 2002
Messages
914
Helped
148
Reputation
292
Reaction score
38
Trophy points
1,308
Location
Germany
Activity points
9,550
If the full adder is

A+B+CIN->S+COUT

set A=FFFFh and B=0000h and CIN=1b

and interchange A and B. With this test you trigger the critical path. Toggling all nodes with a reduced vector set require knowledge about the implementation.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top