How to use xilinx vhdl files in synopsys flow

[pavankumarmnnit]

i.e if a big project in vhdl is done by using xilinx ise simulator then how to add vhdl code to synopsys vcs.

In synopsys vcs coding style is some what different when compared to xilinx.

just compare counter example in both flows, if u consider synopsys u need to define package for increment and then include counter code whereas in xilinx u directly use + 1 to increment.


Any body suggest about compatability between the two......