how to use write_sdf command ?

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quan228228

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write_sdf

hi,
When i sythesis a design and then do a simulation. I found some warning in log when simulating.
Whe warning is like below:

Warning: Timing violation:.................

There are thounds of the warning. Why ? Did i use the comand "write_sdf" wrong in synthesis scripts?
In the scripts"
write_sdf -force_caculation -edges noedge -interconn none -nonegchecks -version2.1 /netlists/ cm3206.vg"

Help me?

Regards
/David
 

sdf generic write_sdf

i think many reasons: 1. you constrain mismatch your simulation invironment . 2. two clock domain

Added after 1 seconds:

i think many reasons: 1. you constrain mismatch your simulation invironment . 2. two clock domain
 

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    quan228228

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write sdf triplet

check whether RST/PRESET etc are asserted /deasserted with proper timing. suggest to assert them on the unused edge of the clock
 

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