Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] How to use vcvs source as OR & AND gates?

Status
Not open for further replies.
dragonfury

dragonfury

Member level 4
Joined
Apr 21, 2007
Messages
69
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,724
Please can you elaborate how to use the vcvs source as OR or AND gate in Cadence? How to connect the terminals?
 

That's a strange request. The vcvs is an awkward component to use for that purpose. Why not just use an OR or AND gate model?
 

VCVS model in the current Cadence 6.15 version has options in its parameter list, i.e. to choose from different behaviors it can perform (vcvs, or, and ). When I choose "or" i expect that it should operate in that manner but it does not. I was wondering if anyone here has used it.

crutschow said:
That's a strange request. The vcvs is an awkward component to use for that purpose. Why not just use an OR or AND gate model?
Click to expand...
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top